1. Field of the Invention
The present invention relates to a control method for controlling a data transfer control unit, and more particularly to a control method for controlling the data transfer so that an upper-level host reads the data from a device such as a hard disk and accepts an interrupt signal from the device.
2. Description of the Prior Art
In recent years, the information electronic apparatuses represented by a mobile phone have widely spread in the world. It is well known that most of the information electronic apparatuses can operate using digital data.
Also, it is well known that such an information electronic apparatus includes a device such as a hard disk. When data is read from the device, or hard disk, an interface for making data transfer is based on standards that can cope with the higher speed due to an increased amount of transfer data. On the host part, for controlling the interface, the CPU carries out the control of the data transfer process. However, due to a request for a higher data transfer rate, a throughput (amount of job (work) processible per unit of time by the computer) in the data transfer is decreased. This becomes serious under the influence of a transfer control process carried out by the host.
The conventional data transfer control unit was disclosed in Japanese Patent Laid-Open No. 07-013898 or Japanese Patent Laid-Open No. 11-345091, for example. Referring to FIGS. 1 to 6, the conventional data transfer control unit will be described below. FIGS. 1 to 3 show a data transfer control unit in the conventional example, and FIGS. 4 to 6 show another data transfer control unit in the conventional example. And FIG. 1 is a block diagram showing the configuration of the data transfer control unit in the conventional example, FIG. 2 is a flowchart showing the operation of the data transfer control unit in the conventional example, and FIG. 3 is a timing chart showing the signal operation for the data transfer control unit in the conventional example. Also, FIG. 4 is a block diagram showing the configuration of another data transfer control unit in the conventional example, FIG. 5 is a flowchart showing the operation of another data transfer control unit in the conventional example, and FIG. 6 is a timing chart showing the signal operation for another data transfer control unit in the conventional example.
As shown in FIG. 1, LSI 1 is an upper-level host, i.e., a personal computer that comprises a CPU 10 as the control unit, and an ATA (AT Attachment) host controller 3 for controlling the operation of an ATA (AT Attachment)/ATAPI (AT Attachment Packet Interface) device 2 such as a hard disk or a CD-ROM drive. And, a process for reading the data from a storage medium within the ATA/ATAPI device 2 via the ATA host controller 3, or a data transfer process, is executed upon a command from the CPU 10.
In FIG. 2, steps A1 to A6 and A8 involve a control process of the CPU 10 for the ATA host controller 3 located inside the LSI 1. Also, steps B1, B2 and B7 involve a control process of the ATA host controller 3. Herein, data transfer, as used in this invention, means transferring data, especially when the upper-level host 1 reads the data from the ATA/ATAPI device 2.
Step A1 is a process for the CPU 10 to set the parameters required for the data transfer, including a start sector number, a sector size, a data size and a mode in the data transfer, on the ATA/ATAPI device 2 for performing the data transfer process.
Step A2 is a process for the CPU 10 to set the parameters required for the data transfer, including a data size and a mode in the data transfer to the ATA/ATAPI device 2 for performing the data transfer process on the ATA host controller 3.
Step A3 is a process for the CPU 10 to write a command for starting the actual transfer process by the parameters set at step A1 via the ATA host controller 3 into the ATA/ATAPI device 2.
Step A4 is a process for confirming the ATA/ATAPI device 2 of processing object as to whether or not the ATA/ATAPI device 2 has normally accepted the start of transfer process for the step A3.
Step A5 is a process for setting the ATA host controller 3 to a data transfer mode (read mode) to enable the ATA host controller 3 to start reading the data.
And step A6 is a process for detecting an interrupt signal from the ATA/ATAPI device 2, while the CPU 10 is reading the data from the ATA/ATAPI device 2 via the ATA host controller 3.
Then, the ATA/ATAPI device 2 issues an interrupt signal, after transferring the total data of a predetermined reading capacity to the ATA host controller 3.
Step A8 is a process for detecting whether or not the transferred data resides in a buffer memory 6 laid in the ATA host controller 3, namely, reading the value of a register indicating a state of the buffer memory 6. Then, at step A9, it is determined whether or not the state of the buffer memory 6 is empty, as a result of processing at step A8. If the state of the buffer memory 6 is empty, an interrupt process is enabled (not shown). Then, a transfer end process is performed.
The ATA host controller 3 switches to the data transfer mode at step B1 by accepting an instruction of step A5 from the CPU 10. That is, the ATA host controller 3 is switched to the data transfer mode.
At step B2, the ATA host controller 3 performs the data transfer process for reading the data from the ATA/ATAPI device 2 in accordance with the ATA protocol. Then, at step B7, a determination is made whether or not step B2 is repeated up to the data size set at step A2. In this manner, the LSI1, as the host, reads the data from the ATA/ATAPI device 2.
However, the prior art had the following disadvantages. That is, the data transfer rate is decreased owing to a polling process for the state of the ATA host controller 3 from the CPU 10 at steps A8 and A9, until it is recognized that the state of the buffer memory 6 in the ATA host controller 3 is empty at step A9.
That is, since a data signal 17 on a CPU bus 9 is attended with a cycle D8 in the polling process, as shown in a timing chart of FIG. 3, the cycle D8 and the data transfer cycle take place on the CPU bus 9 at the same time, resulting in the problem that the data transfer rate is decreased.
Also, in the prior art, the CPU 10 may not start the polling process for the state of the buffer memory 6 immediately, but may wait for a fixed time after the ATA/ATAPI device 2 issues the interrupt signal to begin the polling process.
In this case, however, due to a difference in the size of the buffer 6 for the ATA host controller 3 or the transfer rate of the CPU bus 9, it is required to individually set the timing from the recognition of an interruption to the start of the polling process for the buffer state. When the ATA host controller 3 is diverted to some other system, there is the disadvantage that the portability (transplantation) of a control program is lost because the processing method is different depending on the system.
In order to solve the above-mentioned problems, a means for laying a mask circuit 13 for masking an interrupt signal 12 input into the ATA/ATAPI device 2 till the end of transfer in the ATA host controller 16 is employed in the conventional example, as shown in FIG. 4. By using an EMPTY signal 14 (see FIG. 4) that is output from the buffer memory 6 indicating that the buffer is empty, the interrupt signal 12 output from the ATA/ATAPI device 2 is controlled. That is, based on the interrupt signal 12 from the ATA bus in FIG. 6, an interrupt signal 20 is output to the CPU bus 9 when an FIFO EMPTY signal 19 of ATA host controller internal signal is “H”. Accordingly, step B1 for masking the interrupt signal and step B11 for removing the mask of the interrupt signal 12 after step B4 are added in FIG. 5. Hence, it is possible to suppress the polling process at steps A8 and A9 for the ATA host controller 16 from the CPU 10 in FIG. 1 and avoid a decrease in the data transfer rate.
However, with this data transfer method, there is the disadvantage that an interrupt signal can not be recognized until the buffer memory 6 becomes empty. If an interruption due to a data transfer error occurs from the ATA/ATAPI device 2, while the interrupt signal from the ATA/ATAPI device 2 is being masked depending on the state of the buffer memory 6 within the ATA host controller 16, an error process by the CPU 10 is delayed leading to an inconvenience that the system performance is degraded. If the data transfer via the CPU bus 9 is not made for some reason, the interrupt signal is not recognized at all, resulting in a problem that the system is frozen.